A New Shift in Computing Power: FPGAs Regain Industry Influence in AI Inference, as Domestic Substitution Enters a Critical Window

As global AI computing power grapples with structural challenges—stemming from GPU supply shortages, runaway power consumption, and soaring costs—a technology once long relegated to a supporting role—FPGA (field-programmable gate array)—is now undergoing a reevaluation of its value in the burgeoning field of AI inference.

I. Global Market: Steady Growth, with Emerging Structural Opportunities

According to the latest report by MarketsandMarkets, a globally renowned market research firm (report code SE 3058), the global FPGA market is projected to grow from approximately US$11.73 billion in 2025 to US$19.34 billion by 2030, with a compound annual growth rate (CAGR) of 10.5% over this period. This expansion is primarily driven by surging demand for high-performance computing in data centers, telecommunications, and the automotive sectors, while the rapid advancement of AI acceleration, 5G infrastructure, and edge computing is providing strong momentum to the market. Meanwhile, data from another firm, Research and Markets, indicates that the embedded FPGA (eFPGA) market is expanding even more rapidly, expected to increase from US$12.54 billion in 2025 to US$24.9 billion by 2030, at a CAGR of 14.8%. The Asia-Pacific region is forecast to be the fastest-growing market, supported by the development of telecommunications infrastructure and the digital transformation of the AI industry in countries such as China, Japan, and South Korea.

From a competitive landscape perspective, the global FPGA market is highly concentrated. AMD (Xilinx) leads with approximately 51% of the market share and boasts the industry‑leading 7nm Versal platform. Following Silver Lake’s $8.75 billion acquisition of a 51% stake in Intel’s Altera in 2025, Altera became the world’s largest independent FPGA company, while the four major U.S. vendors collectively account for over 90% of the global market.

II. The Strategic Value of FPGAs in AI Inference Has Been Reassessed

The demand structure for AI computing power is undergoing a fundamental shift. According to industry data, by 2026, inference workloads are expected to account for more than 65% of total data center compute capacity. This transition signifies that the market’s criteria for evaluating compute chips are shifting from an exclusive focus on peak floating-point operations per second (FLOPS) to a greater emphasis on latency, energy efficiency, and overall total cost of ownership.

In this transformation, the unique advantages of FPGAs are becoming increasingly evident. Large language model inference scenarios are characterized by rapid algorithmic iteration, stringent low‑latency requirements, and highly fragmented workloads—precisely the attributes that highlight FPGA’s core strengths: first, reconfigurability, enabling swift adaptation to algorithmic updates and protocol upgrades without incurring the high tape‑out costs and long lead times associated with ASICs; second, hardware‑level low latency, with an end‑to‑end latency in a parallel execution architecture that significantly outperforms GPU‑based instruction‑scheduling approaches, making it ideally suited for real‑time inference; and third, scenario‑specific energy efficiency, eliminating redundant computations in specific workloads and delivering a markedly superior energy‑efficiency ratio compared to general‑purpose GPUs.

Cutting-edge research further corroborates this trend. A recent study, XtraMAC, published on arXiv, demonstrates that a mixed-precision inference approach for large language models, evaluated on an AMD Xilinx U55c FPGA, achieves 1.4 to 2.0 times higher computational density, reduces LUT, FF, and DSP utilization per operation by 27% to 51%, and improves energy efficiency by up to 1.9×.

In early 2026, at NVIDIA’s GTC conference, the Groq 3 LPX AI inference accelerator rack was unveiled, officially cementing the FPGA’s status as a core standard component in high‑end AI inference architectures. Each tray is equipped with a single FPGA serving as the central scheduler and supporting element, and each rack requires 32 FPGAs. This architectural design is regarded as a landmark milestone, marking the FPGA’s evolution from an edge‑level auxiliary role to a pivotal pillar of AI computing infrastructure.

At the software ecosystem level, Altera (formerly Intel’s Programmable Solutions Group) released FPGA AI Suite version 26.1.1 in April 2026, introducing a brand-new spatial compiler architecture. This compiler can map neural networks directly to the FPGA hardware layer, replacing traditional serial processing with stream‑based dataflow computation, thereby delivering AI inference performance comparable to that of ASICs while ensuring deterministic behavior and low latency. Meanwhile, AMD Xilinx continues to deepen its deployment of Versal adaptive SoCs in AI applications, seamlessly integrating the AI Engine, programmable logic, processor system, and on‑chip network.

III. Technical Bottlenecks: The Trade-offs Between the Advantages and Costs of Reconfigurability

FPGAs are far from a “universal solution,” and their large-scale deployment still faces significant technical and ecosystem barriers. The most fundamental challenge lies in programming complexity. Traditional FPGA development relies on RTL design languages (Verilog/VHDL), requiring developers to master hardware‑level skills such as digital circuit design and timing analysis, which results in a steep learning curve. By contrast, GPUs benefit from a mature CUDA ecosystem and well‑established Python frameworks, enabling developers to deploy AI models without delving into low‑level hardware details. Industry observers note that FPGA‑based implementations typically take three to five times longer than software‑based approaches, and advanced FPGA engineers remain in critically short supply in the domestic market.

The second challenge is the pressure to catch up in process technology. Leading international manufacturers have already ramped up mass production of FPGA products based on 7nm and more advanced nodes, whereas China’s mainstream FPGAs remain concentrated at 28nm and above, leaving a noticeable gap in terms of logic density, power‑consumption control, and high‑speed interface performance. Today, top‑tier international products support 112 Gbps SerDes and PCIe 5.0/6.0, while most domestic offerings are still stuck at PCIe 4.0 and 25 Gbps levels. Moreover, in 3D packaging, both static and dynamic power consumption of FPGAs can become thermal‑management bottlenecks, thereby impacting the cost‑performance ratio of bridge chips.

The third challenge lies in the maturity of the EDA toolchain. Xilinx’s Vivado and Altera’s Quartus, after more than a decade of iterative development, have established comprehensive IP libraries and robust third-party support ecosystems. By contrast, domestic EDA tools still lag behind in areas such as timing‑closure analysis accuracy, automated place-and-route, and high‑level synthesis optimization.

However, the industry is actively addressing these bottlenecks. High-level synthesis tools and open-source frameworks such as TVM are gradually lowering the barrier to FPGA programming, while the rise of AI-native development platforms is taking this trend to a new stage. Gartner has identified AI-native development platforms as a top architectural trend for 2026, with FPGA/EDA toolchains set to be fully integrated into this ecosystem. By leveraging large models, these platforms enable automated workflows, significantly shortening development cycles.

IV. Domestic Substitution: From “Mid- to Low-End Penetration” to “High-End Breakthrough”

In this wave of technological advancement, domestically produced FPGAs are poised to seize a historic opportunity.

As one of the world’s largest FPGA markets, China is projected by Gartner to account for 68% of the global FPGA market by 2025. However, the domestic FPGA market remains largely dominated by companies such as Xilinx (AMD), Altera (Intel), and Lattice, with Chinese brands holding only a 15% market share—concentrated in low‑end products built on processes at 28 nm or larger and featuring fewer than 200,000 logic elements. Meanwhile, another set of data indicates that the domestic FPGA penetration rate has risen from 9% in 2020 to 27% by 2025; yet critical components, such as high‑speed SerDes IP, still face significant gaps in import substitution.

In recent years, driven by both supply-chain security and the push for computational‑power self‑reliance, the pace of domestic substitution has accelerated markedly. Today, four Chinese companies—Unisoc Tongchuang, Zhongwei Yixin, Fudan Microelectronics, and Elinx—are capable of developing FinFET FPGA chips at the billion‑gate scale. In the automotive‑grade segment, numerous domestic FPGA vendors have obtained ISO 26262 ASIL‑D/B certifications, supporting applications such as ADAS sensor pre‑processing and domain‑controller redundancy logic. Meanwhile, in edge‑AI deployments, domestic manufacturers are entering the market with low‑cost, low‑power solutions, leveraging programmability to deliver hardware acceleration for convolution, quantization, and other computational operators.

However, objectively speaking, the gap between domestic FPGAs and international industry leaders remains substantial: Xilinx and Intel have long since ramped up mass production of 7nm‑class high‑end products and established comprehensive EDA toolchains and IP ecosystems, whereas domestic manufacturers still primarily rely on 28nm technology. As a result, their high‑speed interface performance and chip compute density lag behind, and their ecosystem exhibits significant shortcomings. This means that, at this stage, domestically produced FPGAs will require considerable time to replace foreign solutions in advanced applications such as high‑end AI inference racks; for now, the market is largely concentrated in mid‑to‑low‑end edge inference, government and enterprise‑specific customizations, and the existing market for domestic substitution.

V. Future Outlook: FPGAs Emerge as a Core Component of “Elastic Computing Power”

Looking ahead, FPGAs will not replace GPUs or ASICs, but their role in heterogeneous computing architectures will become increasingly critical. In the cloud, FPGAs provide elastic capabilities for data‑stream preprocessing, network acceleration, and inference acceleration; at the edge, their low latency and high determinism make them indispensable enablers for hard‑real‑time applications such as industrial control and autonomous driving; and on the chip‑frontend, FPGAs remain an essential tool for prototyping and verification of ASICs and SoCs.

FPGA’s strategic position in AI inference has been widely recognized by the mainstream industry, and the sector’s growth ceiling is now undergoing a substantive upward shift. Within China’s current historic window—marked by efforts to achieve domestic computing power independence and breakthroughs in indigenous FPGA technology—the trajectory of the industry will ultimately hinge on three key factors: the maturity of the EDA toolchain, continuous advancements in process technology, and the systematic development of a robust developer ecosystem. Each incremental step in these three areas will directly determine whether domestically produced FPGAs can evolve from “usable” to “easy to use.”