An Overview of Emerging Non-Volatile Memory Technologies
- Why We Need a New Type of Non-Volatile Memory
Traditional storage systems face a fundamental trade-off: the faster the speed, the higher the cost, and they typically cannot retain data when power is cut off.
SRAM: Fastest speed (~1 ns), but requires 6 transistors to store 1 bit, resulting in large area and high cost.
DRAM: Relatively fast (~50 ns), but requires continuous refreshing and loses data when power is cut off.
NAND Flash: Non-volatile and high-density, but slow write speeds (~100 μs) and limited erase/write endurance.
The explosive growth of large AI models, in-vehicle devices, and smart terminals has created entirely new demands for storage: low latency, low power consumption, non-volatility, high density, and a wide operating temperature range. At the same time, the energy consumption bottleneck caused by data transfer—a result of the “separation of storage and computation” in the von Neumann architecture—is becoming increasingly prominent.
II. Detailed Explanation of the Four Major Emerging NVM Technologies
According to a technical review presented by Dr. Masatoshi Yoshikawa of Kioxia’s Advanced Technology Research Institute at the 2026 IEEE VLSI Conference, the four most promising emerging NVM technologies each have their own distinct focus.
1. STT-MRAM (Spin-Transfer Torque Magnetoresistive Random Access Memory)
Working Principle. At the core of STT-MRAM is the magnetic tunneling junction (MTJ)—composed of two layers of magnetic material sandwiching an insulating layer. One layer of magnetic material has a fixed magnetization direction (reference layer), while the other can be flipped (free layer). When the magnetization directions of the two layers are parallel, the resistance is low (representing “0”); when they are antiparallel, the resistance is high (representing “1”).
Key Breakthroughs. Early Al2O3-based MTJs had a tunnel magnetoresistance (TMR) ratio of less than 200%, which limited the strength of the read signal. In 2023, MgO-based MTJs increased the TMR to 631%, laying the foundation for the practical application of STT-MRAM.
Performance Characteristics. With read and write speeds approaching those of SRAM while offering non-volatility, it is an emerging NVM with the best overall performance. There is a trade-off between write power consumption and speed—high-speed writing requires higher current, which may damage the tunneling barrier.
Application Scenarios. It covers a full range of scenarios, from CPU caches and automotive embedded systems to standalone high-capacity storage. Embedded STT-MRAM (eMRAM) is considered the preferred embedded NVM solution for edge AI devices.
Latest Developments. A paper presented at the 2026 IEEE ISSCC demonstrated a 16nm 168Mb embedded STT-MRAM with a bit cell area reduced to 0.0249 μm², supporting dual-port access and achieving a read throughput of 51.2 Gb/s, designed for automotive and edge AI applications.
2. ReRAM (Resistive Random-Access Memory)
Principle of Operation. ReRAM changes its resistance state by applying a voltage to an oxide film to form or break a conductive filament. When the filament is formed, the resistance is low (“1”); when it breaks, the resistance is high (“0”).
Technical Approaches. There are two main categories: oxide-based and metal-bridge approaches.
Bottlenecks and Challenges: Resistance Fluctuations: The formation and breakage of conductive filaments are random, leading to fluctuations in resistance values. Retention: Conductive filaments may naturally degrade over time, affecting data retention time. Latency: Write speeds are slower than those of STT-MRAM
Advantages. The 1S1R cross-array configuration enables extremely high storage density. Bulk-ReRAM/VCMO-ReRAM solutions without conductive wires are being developed to reduce resistance fluctuations and RTN noise, but they remain in the R&D phase and have not yet entered mass production.
3. FeRAM (Ferroelectric Random-Access Memory)
Working Principle. FeRAM utilizes the polarization characteristics of ferroelectric materials to store data. When an electric field is applied, the polarization direction of the ferroelectric material reverses, and the polarization state remains unchanged after the electric field is removed—thus enabling non-volatile storage.
Technical Architecture. There are three implementation architectures: 1T1C, FeFET, and FTJ. In terms of materials, there has been an evolution from traditional perovskite-based ferroelectric materials to HfO₂-based ferroelectric materials, the latter of which offers better compatibility with CMOS processes.
Features. Fast write speeds and low power consumption, but challenges include destructive read operations (where reading alters the storage state, requiring rewriting) and 3D stacking processes.
4. PCM (Phase-Change Memory) and SOM
Working Principle. PCM utilizes the reversible phase transition between the crystalline state (low resistance) and the amorphous state (high resistance) of chalcogenide compounds (such as GeSbTe alloys) to store data.
Bottlenecks:
Resistance Drift: The resistance of the amorphous state changes slowly over time, affecting read reliability.
OTS Selector: Requires high-performance gate drivers to suppress leakage current.
SOM : A new type of dielectric-free stacking technology that uses the selector itself as the storage medium.
Market Status. PCM faces difficulties in porting to advanced process nodes (such as FinFET) and is gradually being marginalized.
END
MRAM and RRAM are considered the most promising successors in the NVM field. The two technologies will coexist for the long term, each with its own focus—MRAM emphasizes speed and endurance (cache, embedded applications), while RRAM emphasizes density and cost (high-capacity storage).
By 2031, the combined market size of embedded RRAM, MRAM, and PCM is projected to exceed $4 billion. Of this total, MRAM revenue is projected to reach approximately $1.1 billion, while RRAM revenue is expected to approach $900 million.
In the standalone memory sector, growth momentum has slowed somewhat since Intel’s exit from 3D XPoint; however, in the embedded sector, the adoption rate of eMRAM, ePCM, and eReRAM in MCUs, SoCs, and ASICs continues to rise. Experts point out that MRAM/ReRAM is fully ready to replace NOR in one-third to one-quarter of the area, providing XIP (eXecute-in-Place) and instant-on capabilities, which perfectly align with the low-power requirements of edge AI and IoT.
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